TriLevel Cache Design

• Enables the desktop PC industry's largest total system cache
• 320KB total internal cache
• Internal 64KB Level 1 cache (32KB instruction cache and 32KB write-back dual-ported data cache)
• Internal, full-speed backside 256KB Level 2 write-back cache
• Multiport internal cache design enabling simultaneous 64-bit reads/writes of L1 and L2 caches
• 4-way set associative L2 cache design enabling optimal data management and efficiency
• 100-MHz frontside bus to an optional external Level 3 cache on Super7™ motherboard

3DNow!™ technology

• 21 new SIMD instructions to improve 3D graphics and multimedia performance
• Peak operation of 4 floating point operations per clock
• Separate multiplier and ALU for superscalar instruction execution
• Compatible with existing x86 operating system

Compatible with high performance, cost effective Super7 platform

• Supports high-speed 100-MHz processor bus
• Accelerated Graphics Port (AGP) support

Enhanced superscalar MMX™ instruction execution with dual decode and dual execution pipelines
High-performance IEEE 754- and 854-compatible floating-point unit (FPU)
Industry-standard system management mode (SMM)
x86 binary software compatibility
Die size: 21.3 million transistors on 118 mm2 die
Available in 321-pin Ceramic Pin Grid Array (CPGA) package (Super7 platform compatible) using innovative C4 flip-chip technology
Manufactured using AMD's state-of-the-art 0.25-micron, five-layer-metal silicon process technology and local interconnect technology at AMD's Fab 25 wafer fabrication facility